1. Field of the Invention
The present invention relates to a static random access memory (SRAM) and particularly relates to a configuration of a write/read circuit and a structure of a bit line to which write/read data is transferred.
2. Description of the Related Art
An SRAM is a kind of a writable/readable memory (RAM) by random access and employs a flip-flop circuit or the like as a storage element. In recent years, it has been increasingly difficult to develop stably operating SRAMs following downsizing of integrated circuits.
If a magnitude of wirings (a design rule) forming the SRAM is made small, an irregularity in threshold voltage becomes conspicuous among transistors constituting the flip-flop circuit. This results in operation failures such as deterioration in stability of various operations performed by the SRAM and deterioration in writing characteristic. Particularly for the SRAM, improvement in stability and improvement in writing characteristic are in a tradeoff relationship. For this reason, it is disadvantageously quite difficult to improve both the stability and the writing characteristic.
To solve the problem, there is known a method of dividing a bit line used to write or read data to or from a storage element into a plurality of bit lines and further providing a dedicated bit line for data transfer, as disclosed in Japanese Patent Application Laid-Open No. 59-165292. The method disclosed in the Japanese Patent Application Laid-Open No. 59-165292 has the following problems. An area of peripherals of memory cells disadvantageously increases, thus deteriorating area efficiency of the entire SRAM.
For these reasons, it is disadvantageously difficult to downsize the SRAM so as to improve operation stability and writing characteristic according to the conventional technique.